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1 of 19 062299 features 4096 bits electrically erasable programmable read only memory (eeprom) unique, factory-lasered and tested 64-bit registration number (8-bit family code + 48- bit serial number + 8-bit crc tester) assures absolute identity because no two parts are alike built-in multidrop controller ensures compatibility with other microlan products memory partitioned into sixteen 256-bit pages for packetizing data 256-bit scratchpad with strict read/write protocols ensures integrity of data transfer reduces control, address, data and power to a single data pin directly connects to a single port pin of a microprocessor and communicates at up to 16.3k bits per second overdrive mode boosts communication speed to 142k bits per second 8-bit family code specifies ds2433 communication requirements to reader presence detector acknowledges when reader first applies voltage low cost pr-35 or 8-pin soic surface mount package reads and writes over a wide voltage range of 2.8v to 6.0v from -40c to +85c pin assignment pin description pr-35 soic pin 1 ground nc pin 2 data nc pin 3 nc data pin 4 -- ground pin 5-8 -- nc ordering information ds2433 pr-35 package ds2433s 8-pin soic package DS2433T tape & reel version of ds2433 ds2433y tape & reel version of ds2433s ds2433x chip scale pkg., tape & reel silicon label description the ds2433 4k-bit 1-wire eeprom identifies and stores relevant information about the product to which it is associated. this lot or product specific information can be accessed with minimal interface, for example a single port pin of a microcontroller. the ds2433 con sists of a factory-lasered registration number that includes a unique 48-bit serial number, an 8-bit crc, and an 8-bit family code (23h) plus 4096 bits of user-programmable eeprom. the power to read and write the ds2433 is derived entirely ds2433 4k-bit 1-wire tm eeprom preliminary www.dalsemi.com nc nc data gnd nc 2 3 4 8 7 6 5 1 8-pin soic (208 mil) nc nc nc 1 2 3 3 2 1 pr-35 bottom view
ds2433 2 of 19 from the 1-wire communication line. the memory is organized as sixteen pages of 256 bits each. the scratchpad is an additional page that acts as a buffer when writing to memory. data is first written to the scratchpad where it may be read back for verification. a copy scratchpad command will then transfer the data to memory. this process insures data integrity when modifying the memory. the 64-bit registration number provides a guaranteed unique identity which allows for absolute traceability and acts as node address if multiple ds2433 are connected in parallel to form a local network. data is transferred serially via the 1-wire protocol which requires only a single data lead and a ground return. the pr-35 and soic packages provide a compact enclosure that allows standard assembly equipment to handle the device easily for attachment to printed circuit boards or wiring. typical applications include storage of calibration constants, board identification and product revision status. overview the block diagram in figure 1 shows the relationships between the major control and memory sections of the ds2433. the ds2433 has three main data components: 1) 64-bit lasered rom, 2) 256-bit scratchpad, and 3) 4096-bit eeprom. the hierarchical structure of the 1-wire protocol is shown in figure 2. the bus master must first provide one of the six rom function commands, 1) read rom, 2) match rom, 3) search rom, 4) skip rom, 5) overdrive-skip rom or 6) overdrive-match rom. upon completion of an overdrive rom command byte executed at standard speed, the device will enter overdrive mode where all subsequent communication occurs at a higher speed. the protocol required for these rom function commands is described in figure 9. after a rom function command is successfully executed, the memory functions become accessible and the master may provide any one of the four memory function commands. the protocol for these memory function commands is described in figure 7. all data is read and written least significant bit first. parasite power the block diagram (figure 1) shows the parasite-powered circuitry. this circuitry ?steals? power whenever the i/o input is high. i/o will provide sufficient power as long as the specified timing and voltage requirements are met. ds2433 block diagram figure 1
ds2433 3 of 19 64-bit lasered rom each ds2433 contains a unique rom code that is 64 bits long. the first eight bits are a 1-wire family code. the next 48 bits are a unique serial number. the last eight bits are a crc of the first 56 bits. (see figure 3.) the 1-wire crc is generated using a polynomial generator consisting of a shift register and xor gates as shown in figure 4. the polynomial is x 8 + x 5 + x 4 + 1. additional information about the dallas 1-wire cyclic redundancy check is available in the book of ds19xx i button standards. the shift register bits are initialized to zero. then starting with the least significant bit of the family code, one bit at a time is shifted in. after the 8 th bit of the family code has been entered, then the serial number is entered. after the 48 th bit of the serial number has been entered, the shift register contains the crc value. shifting in the eight bits of crc should return the shift register to all zeros. memory the memory map in figure 5 shows a 32-byte page called the scratchpad and additional 32-byte pages called memory. the ds2433 contains pages 0 through 15 which make up the 4096-bit eeprom. the scratch-pad is an additional page that acts as a buffer when writing to memory. address registers and transfer status because of the serial data transfer, the ds2433 employs three address registers, called ta1, ta2 and e/s (figure 6). registers ta1 and ta2 must be loaded with the target address to which the data will be written or from which data will be sent to the master upon a read command. register e/s acts like a byte counter and transfer status register. it is used to verify data integrity with write commands. therefore, the master only has read access to this register. the lower five bits of the e/s register indicate the address of the last byte that has been written to the scratchpad. this address is called ending offset. bit 5 of the e/s register, called pf, is set if the number of data bits sent by the master is not an integer multiple of 8 or if the data in the scratchpad is not valid due to a loss of power. a valid write to the scratchpad will clear the pf bit. bit 6 has no function; it always reads 0. note that the lowest five bits of the target address also determine the address within the scratchpad, where intermediate storage of data will begin. this address is called byte offset. if the target address (ta1) for a write command is 03ch for example, then the scratchpad will store incoming data beginning at the byte offset 1ch and will be full after only four bytes. the corresponding ending offset in this example is 1fh. for best economy of speed and efficiency, the target address for writing should point to the beginning of a new page, i.e., the byte offset will be 0. thus the full 32-byte capacity of the scratchpad is available, resulting also in the ending offset of 1fh. however, it is possible to write one or several contiguous bytes somewhere within a page. the ending offset together with the partial flag support the master checking the data integrity after a write command. the highest valued bit of the e/s register, called aa is valid only if the pf flag reads 0. if pf is 0 and aa is 1, a copy has taken place. the aa bit is cleared when the device receives a write scratchpad command. writing with verification to write data to the ds2433, the scratchpad has to be used as intermediate storage. first the master issues the write scratchpad command to specify the desired target address, followed by the data to be written to the scratchpad. under certain conditions (see write scratchpad command) the master will receive an inverted crc16 of the command, address and data at the end of the write scratchpad command sequence. knowing this crc value, the master can compare it to the value it has calculated itself to decide if the communication was successful and proceed to the copy scratchpad command. if the master could not receive the crc16, it has to send the read scratchpad command to read back the scratchpad to verify data integrity. as preamble to the scratchpad data, the ds2433 repeats the target address ta1 and ta2 and sends the contents of the e/s register. if the pf flag is set, data did not arrive correctly in the
ds2433 4 of 19 scratchpad or there was a loss of power since data was last written to the scratchpad. the master does not need to continue reading; it can start a new trial to write data to the scratchpad. similarly, a set aa flag together with a cleared pf flag indicates that the write command was not recognized by the device. if everything went correctly, both flags are cleared and the ending offset indicates the address of the last byte written to the scratchpad. now the master can continue reading and verifying every data byte. after the master has verified the data, it has to send the copy scratchpad command. this command must be followed exactly by the data of the three address registers ta1, ta2 and e/s. the master may obtain the contents of these registers by reading the scratchpad or derive it from the target address and the amount of data to be written. as soon as the ds2433 has received these bytes correctly, it will copy the data to the requested location beginning at the target address. hierarchcal structure for 1-wire protocol figure 2 64-bit lasered rom figure 3 msb lsb 8-bit crc code 48-bit serial number 8-bit family code (23h) msb lsb msb lsb msb lsb 1-wire crc generator figure 4 input
ds2433 5 of 19 memory function commands the ?memory function flow chart? (figure 7) describes the protocols necessary for accessing the memory. an example follows the flowchart. the communication between master and ds2433 takes place either at regular speed (default, od = 0) or at overdrive speed (od = 1). if not explicitly set into the overdrive mode the ds2433 assumes regular speed. write scratchpad command [0fh] after issuing the write scratchpad command, the master must first provide the 2-byte target address, followed by the data to be written to the scratchpad. the data will be written to the scratchpad starting at the byte offset (t4:t0). the ending offset (e4:e0) will be the byte offset at which the master stops writing data. only full data bytes are accepted. if the last data byte is incomplete its content will be ignored and the partial byte flag pf will be set. when executing the write scratchpad command the crc generator inside the ds2433 (see figure 12) calculates a crc over the entire data stream, starting at the command code and ending at the last data byte sent by the master. this crc is generated using the crc16 polynomial by first clearing the crc generator and then shifting in the command code (0fh) of the write scratchpad command, the target addresses ta1 and ta2 as supplied by the master and all the data bytes. the master may end the write scratchpad command at any time. however, if the ending offset is 11111b, the master may send 16 read time slots and will receive the crc generated by the ds2433. the memory address range of the ds2433 is 0000h to 01ffh. if the bus master sends a target address higher than this, the internal circuitry of the chip will set the seven most significant address bits to zero as they are shifted into the internal address register. the read scratchpad command will reveal the target address as it will be used by the ds2433. the master will identify such address modifications by comparing the target address read back to the target address transmitted. if the master does not read the scratchpad, a subsequent copy scratchpad command will not work since the most significant bits of the target address the master sends will not match the value the ds2433 expects. read scratchpad command [aah] this command is used to verify scratchpad data and target address. after issuing the read scratchpad command, the master begins reading. the first two bytes will be the target address. the next byte will be the ending offset/data status byte (e/s) followed by the scratchpad data beginning at the byte offset (t4: t0). the master may read data until the end of the scratchpad after which the data read will be all logic 1?s. copy scratchpad [55h] this command is used to copy data from the scratchpad to memory. after issuing the copy scratchpad command, the master must provide a 3-byte authorization pattern which can be obtained by reading the scratchpad for verification. this pattern must exactly match the data contained in the three address registers (ta1, ta2, e/s, in that order). if the pattern matches, the aa (authorization accepted) flag will be set and the copy will begin. copy takes 5 ms maximum during which the voltage on the 1-wire bus must not fall below 2.8v. a pattern of alternating 1s and 0s will be received after the data has been copied until a reset pulse is issued by the master. the data to be copied is determined by the three address registers. the scratchpad data from the beginning offset through the ending offset, will be copied to memory, starting at the target address. anywhere from 1 to 32 bytes may be copied to memory with this command.
ds2433 6 of 19 ds2433 memory map figure 5 address register figure 6 read memory [f0h] the read memory command may be used to read the entire memory. after issuing the command, the master must provide the 2-byte target address. after the two bytes, the master reads data beginning from the target address and may continue until the end of memory, at which point logic 1?s will be read. it is important to realize that the target address registers will contain the address provided. the ending offset/data status byte is unaffected. the hardware of the ds2433 provides a means to accomplish error-free writing to the memory section. to safeguard reading data in the 1-wire environment and to simultaneously speed up data transfers, it is recommended to packetize data into data packets of the size of one memory page each. such a packet would typically store a 16-bit crc with each page of data to insure rapid, error-free data transfers that eliminate having to read a page multiple times to determine if the received data is correct or not. (see the book of ds19xx i button standards, chapter 7 or application note 114 for the recommended file structure.) 32-bit intermediate storage scratchpad 32-byte final storage eeprom 32-byte final storage eeprom final storage eeprom 32-byte final storage eeprom address 0000h to 001fh 003fh 01dfh 01ffh 0020h to 0040h to 1fe0h to page 0 page 1 page 2 to page 14 page 15 t7 t6 t5 t4 t3 t2 t1 t0 t15 aa 1) pf e4 e3 e2 e1 e0 t14 t13 t12 t11 t10 t9 t8 target address (ta1) target address (ta2) ending address with data status (e/s) (read only) 1) this bit will always be 0.
ds2433 7 of 19 memory function flow chart figure 7
ds2433 8 of 19 memory function flow chart figure 7 (continued)
ds2433 9 of 19 memory function example example: write two data bytes to memory location 0026 and 0027. read entire memory. master mode data (lsb first) comments tx reset reset pulse (480 - 960 m s) rx presence presence pulse tx cch issue skip rom command tx 0fh issue write scratchpad command tx 26h ta1, beginning offset = 26h tx 00h ta2, address = 00 26h tx <2 data bytes> write 2 bytes of data to scratchpad tx reset reset pulse rx presence presence pulse tx cch issue skip rom command tx aah issue read scratchpad command rx 26h read ta1, beginning offset = 26h rx 00h read ta2, address = 00 26h rx 07h read e/s, ending offset = 7h, flags = 0h rx <2 data bytes> read scratchpad data and verify tx reset reset pulse rx presence presence pulse tx cch issue skip rom command tx 55h issue copy scratchpad command tx 26h tx 00h tx 07h ta1 ta2 author ization code e/s tx wait 5 ms tx reset reset pulse rx presence presence pulse tx cch issue skip rom command tx f0h issue read memory command tx 00h ta1, beginning offset = 0 tx 00h ta2, address = 00 00h rx <512 bytes> read entire memory tx reset reset pulse rx presence presence pulse, done
ds2433 10 of 19 hardware configuration figure 8 *5k w is adequate for reading the ds2433. to write to a single device, a 2.2k w resistor and v pup of at least 4.0v is sufficient. for writing multiple ds2433s simultaneously or operation at low v pup , the resistor should be bypassed by a low-impedance pullup to v pup while the device copies the scratchpad to eeprom. 1-wire bus system the 1-wire bus is a system which has a single bus master and one or more slaves. in all instances the ds2433 is a slave device. the bus master is typically a micro-controller. the discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-wire signaling (signal types and timing). a 1-wire protocol defines bus transactions in terms of the bus state during specific time slots that are initiated on the falling edge of sync pulses from the bus master. for a more detailed protocol description, refer to chapter 4 of the book of ds19xx i button standards. hardware configuration the 1-wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1-wire bus must have open drain or 3-state outputs. the 1-wire port of the ds2433 is open drain with an internal circuit equivalent to that shown in figure 8. a multidrop bus consists of a 1-wire bus with multiple slaves attached. at regular speed the 1-wire bus has a maximum data rate of 16.3k bits per second. the speed can be boosted to 142k bits per second by activating the overdrive mode. the 1-wire bus requires a pullup resistor of approximately 5k w . the idle state for the 1-wire bus is high. if for any reason a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 16 m s (overdrive speed) or more than 120 m s (regular speed), one or more devices on the bus may be reset. transaction sequence the protocol for accessing the ds2433 via the 1-wire port is as follows: initialization rom function command memory function command transaction/data
ds2433 11 of 19 initialization all transactions on the 1-wire bus begin with an initialization sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that the ds2433 is on the bus and is ready to operate. for more details, see the ?1-wire signaling? section. rom function commands once the bus master has detected a presence, it can issue one of the six rom function commands. all rom function commands are eight bits long. a list of these commands follows (refer to flowchart in figure 9): read rom [33h] this command allows the bus master to read the ds2433?s 8-bit family code, unique 48-bit serial number, and 8-bit crc. this command can only be used if there is a single ds2433 on the bus. if more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-and result). the resultant family code and 48-bit serial number will result in a mismatch of the crc. match rom [55h] the match rom command, followed by a 64-bit rom sequence, allows the bus master to address a specific ds2433 on a multidrop bus. only the ds2433 that exactly matches the 64-bit rom sequence will respond to the following memory function command. all slaves that do not match the 64-bit rom sequence will wait for a reset pulse. this command can be used with a single or multiple devices on the bus. skip rom [cch] this command can save time in a single drop bus system by allowing the bus master to access the memory functions without providing the 64-bit rom code. if more than one slave is present on the bus and a read command is issued following the skip rom command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired-and result). search rom [f0h] when a system is initially brought up, the bus master might not know the number of devices on the 1- wire bus or their 64-bit rom codes. the search rom command allows the bus master to use a process of elimination to identify the 64-bit rom codes of all slave devices on the bus. the search rom process is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. the bus master performs this simple, 3-step routine on each bit of the rom. after one complete pass, the bus master knows the contents of the rom in one device. the remaining number of devices and their rom codes may be identified by additional passes. see chapter 5 of the book of ds19xx i button standards for a comprehensive discussion of a search rom, including an actual example. overdrive skip rom [3ch] on a single-drop bus this command can save time by allowing the bus master to access the memory functions without providing the 64-bit rom code. unlike the normal skip rom command the overdrive skip rom sets the ds2433 in the overdrive mode (od = 1). all communication following
ds2433 12 of 19 this command has to occur at overdrive speed until a reset pulse of minimum 480 m s duration resets all devices on the bus to regular speed (od = 0). when issued on a multidrop bus this command will set all overdrive-supporting devices into overdrive mode. to subsequently address a specific overdrive-supporting device, a reset pulse at overdrive speed has to be issued followed by a match rom or search rom command sequence. this will speed up the time for the search process. if more than one slave supporting overdrive is present on the bus and the overdrive skip rom command is followed by a read command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wire-and result). overdrive match rom [69h] the overdrive match rom command, followed by a 64-bit rom sequence transmitted at overdrive speed, allows the bus master to address a specific ds2433 on a multidrop bus and to simultaneously set it in overdrive mode. only the ds2433 that exactly matches the 64-bit rom sequence will respond to the subsequent memory function command. slaves already in overdrive mode from a previous overdrive skip or match command will remain in overdrive mode. all overdrive-capable slaves will return to regular speed at the next reset pulse of minimum 480 m s duration. the overdrive match rom command can be used with a single or multiple devices on the bus.
ds2433 13 of 19 rom functions flow chart figure 9 (first part)
ds2433 14 of 19 rom functions flow chart figure 9 (continued)
ds2433 15 of 19 1-wire signaling the ds2433 requires strict protocols to insure data integrity. the protocol consists of four types of signaling on one line: reset sequence with reset pulse and presence pulse, write 0, write 1 and read data. all these signals except presence pulse are initiated by the bus master. the ds2433 can communicate at two different speeds, regular speed and overdrive speed. if not explicitly set into the overdrive mode, the ds2433 will communicate at regular speed. while in overdrive mode the fast timing applies to all wave forms. the initialization sequence required to begin any communication with the ds2433 is shown in figure 10. a reset pulse followed by a presence pulse indicates the ds2433 is ready to send or receive data given the correct rom command and memory function command. the bus master transmits (tx) a reset pulse (t rstl , minimum 480 m s at regular speed, 48 m s at overdrive speed). the bus master then releases the line and goes into receive mode (rx). the 1-wire bus is pulled to a high state via the pullup resistor. after detecting the rising edge on the data pin, the ds2433 waits (t pdh , 15-60 m s at regular speed, 2-6 m s at overdrive speed) and then transmits the presence pulse (t pdl , 60-240 m s at regular speed, 8-24 m s at overdrive speed). a reset pulse of 480 m s or longer will exit the overdrive mode returning the device to regular speed. if the ds2433 is in overdrive mode and the reset pulse is no longer than 80 m s the device will remain in overdrive mode. read/write time slots the definitions of write and read time slots are illustrated in figure 11. all time slots are initiated by the master driving the data line low. the falling edge of the data line synchronizes the ds2433 to the master by triggering a delay circuit in the ds2433. during write time slots, the delay circuit determines when the ds2433 will sample the data line. for a read data time slot, if a ?0? is to be transmitted, the delay circuit determines how long the ds2433 will hold the data line low overriding the 1 generated by the master. if the data bit is a ?1?, the device will leave the read data time slot unchanged. initialization procedure reset and presence pulses figure 10 *in order not to mask interrupt signalling by other devices on the 1-wire bus, t rstl + t r should always be less than 960 s. ** includes recovery time.
ds2433 16 of 19 read/write timing diagram figure 11 write-one time slot write-zero time slot read-data time slot crc generation with the ds2433 there are two different types of crcs (cyclic redundancy checks). one crc is an 8- bit type and is stored in the most significant byte of the 64-bit rom. the bus master can compute a crc
ds2433 17 of 19 value from the first 56 bits of the 64-bit rom and compare it to the value stored within the ds2433 to determine if the rom data has been received error-free by the bus master. the equivalent polynomial function of this crc is: x 8 + x 5 + x 4 + 1. this 8-bit crc is received in the true (non-inverted) form when reading the rom of the ds2433. it is computed at the factory and lasered into the rom. the other crc is a 16-bit type, generated according to the standardized crc16-polynomial function x 16 + x 15 +x 2 + 1. this crc is used for fast verification of a data transfer when writing to the scratchpad. it is the same type of crc as is used with nv ram based i buttons for error detection within the i button extended file structure. in contrast to the 8-bit crc, the 16-bit crc is always returned or sent in the complemented (inverted) form. a crc-generator inside the ds2433 chip (figure 12) will calculate a new 16-bit crc as shown in the command flow chart of figure 7. the bus master compares the crc value read from the device to the one it calculates from the data and decides whether to continue with an operation. with the write scratchpad command the crc is generated by first clearing the crc generator and then shifting in the command code, the target addresses ta1 and ta2 and all the data bytes. the ds2433 will transmit this crc only if the data bytes written to the scratchpad include scratchpad ending offset 11111b. the data may start at any location within the scratchpad. for more details on generating crc values including example implementations in both hardware and software, see the book of ds19xx i button standards. crc-16 hardware description and polynomial figure 12 (polynomial x 16 + x 15 + x 2 + 1)
ds2433 18 of 19 absolute maximum ratings* voltage on any pin relative to ground -0.5v to +7.0v operating temperature -40 c to +85 c storage temperature -55 c to +125 c soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. dc electrical characteristics (v pup =2.8v to 6.0v; -40c to +85c) parameter symbol min typ max units notes logic 1 v ih 2.2 v 1, 8 logic 0 v il -0.3 +0.8 v 1, 9 output logic low @ 4 ma v ol 0.4 v 1 output logic high v oh v pup 6.0 v 1, 2 input load current i l 5 m a 3 programming current i lprog 500 m a 10 capacitance (t a = 25c) parameter symbol min typ max units notes i/o (1-wire) c in/out 100 800 pf 6 endurance (v pup =5.0v; t a = 25 c) parameter symbol min typ max units notes write/erase cycles n cycle 50k 11 ac electrical characteristics regular speed (v pup =2.8v to 6.0v; -40 c to +85 c) parameter symbol min typ max units notes time slot t slot 60 120 m s write 1 low time t low1 1 15 m s write 0 low time t low0 60 120 m s read low time t lowr 1 15 m s read data valid t rdv exactly 15 m s release time t release 0 15 45 m s read data setup t su 1 m s 5 recovery time t rec 1 m s reset time high t rsth 480 m s 4 reset time low t rstl 480 m s 7 presence detect high t pdhigh 15 60 m s presence detect low t pdlow 60 240 m s
ds2433 19 of 19 ac electrical characteristics overdrive speed (v pup =2.8v to 6.0v;-40 c to +85 c) parameter symbol min typ max units notes time slot t slot 6 16 m s write 1 low time t low1 1 2 m s write 0 low time t low0 6 16 m s read low time t lowr 1 2 m s read data valid t rdv exactly 2 m s release time t release 0 1.5 4 m s read data setup t su 1 m s 5 recovery time t rec 1 m s reset time high t rsth 48 m s 4 reset time low t rstl 48 80 m s presence detect high t pdhigh 2 6 m s presence detect low t pdlow 8 24 m s notes: 1. all voltages are referenced to ground. 2. v pup = external pullup voltage. 3. input load is to ground. 4. an additional reset or communication sequence cannot begin until the reset high time has expired. 5. read data setup time refers to the time the host must pull the 1-wire bus low to read a bit. data is guaranteed to be valid within 1 m s of this falling edge. 6. capacitance on the data pin could be 800 pf when power is first applied. if a 5 k w resistor is used to pull up the data line to v pup , 5 m s after power has been applied the parasite capacitance will not affect normal communications. 7. the reset low time (t rstl ) should be restricted to a maximum of 960 m s, to allow interrupt signaling, otherwise, it could mask or conceal interrupt pulses. 8. v ih is a function of the external pullup resistor and v pup . 9. under certain low voltage conditions v ilmax may have to be reduced to as much as 0.5v to always guarantee a presence pulse. 10. the copy scratchpad takes 5 ms maximum during which the voltage on the 1-wire bus must not fall below 2.8v. 11. during the execution of the copy scratchpad command the ds2433 automatically erases the memory locations to be written to. no extra steps need to be taken by the bus master.

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